Workshop 8: All Day Friday


Workshop Co-Chairs:

Dror Feitelson, Hebrew University
Larry Rudolph, MIT

Program Committee:
Andrea Arpaci-Dusseau, Stanford
Stephen Booth, EPCC
Allen Downey, Colby College
Allan Gottlieb, NYU
Atsushi Hori, RWCP
Phil Krueger, Sequent
Richard Lagerstrom, Cray Research
Miron Livny, University of Wisconsin
Virginia Lo, University of Oregon
Reagan Moore, SDSC
Bill Nitzberg, NASA Ames
Uwe Schwiegelshohn, University of Dortmund
Ken Sevcik, University of Toronto
Mark Squillante, IBM Research
John Zahorjan, University of Washington
Songnian Zhou, Platform Computing

As parallel computers become more common, scheduling strategies become important as a means of balancing the need for exclusive use of the machine's resources and the desire to make these resources readily available to many diverse users and applications. Moreover, this has to be done in an interactive setting while also coordinating the use of multiple non-CPU resources.

Continuing the tradition established at IPPS'95, the workshop is intended to attract people from academia, supercomputing centers and national laboratories and parallel computer vendors who will address resource management issues in multitasking parallel systems. The workshop will provide an opportunity to attempt to resolve conflicting goals such as short response times for interactive work, minimal interference with batch jobs, fairness to all users, and high system utilization. We hope to achieve a balance among various inputs including: reports on current practices covering the entire range of systems from large and heavily-used installations to the desktop; proposals for novel schemes that have not yet been tested in a real environment; and realistic models and analysis. The emphasis will be on practical designs in the context of real (parallel) operating systems.

Topics of interest include:
- Benchmarking and performance metrics to compare scheduling schemes
- Experience with scheduling policies on current systems
- Optimization of multiple-resource scheduling (e.g., memory too)
- Scheduling on SMPs, scalable SMP systems, and clusters
- Workload characterization and classification
- Fairness, priorities, and accounting issues
- Load estimation and load balancing
- Scheduling on heterogeneous nodes (e.g., with different amounts of memory)
- Support for different classes of jobs (e.g., interactive vs. batch)
- Time slicing and gang scheduling
- Effect of scheduling strategies on application performance
- Interaction of scheduling with memory management and I/O

Advance Program:
A detailed advance program will be available on the workshop home page by
mid February. See URL

In previous years, post-workshop proceedings were published by
Springer-Verlag in the Lecture Notes in Computer Science Series, as Volumes
949, 1162, 1291, and 1459. For full contents and ordering information, see

For more information contact:

Dror Feitelson
Institute of Computer Science
The Hebrew University
91904 Jerusalem, Israel
Vox: +972 2 658 4115

Workshop 9: All Day Friday


Program Chair:
Yi Pan, University of Dayton, USA

Program Vice Chair:
Keqin Li, State University of New York, USA

Program Committee:
Selim G. Akl, Queen's University, Canada
Pierre Chavel, Institut d'Optique Theorique et Appliquee, France
Hyeong-Ah Choi, George Washington University, USA
Marc Desmulliez, Heriot Watt University, UK
Patrick Dowd, University of Maryland, USA
Hossam ElGindy, The University of Newcastle, Australia
Joseph W. Goodman, Stanford University, USA
Mounir Hamdi, Hong Kong University of Science and Technology, Hong Kong
Ahmed Louri, University of Arizona, USA
Philippe J. Marchand, UCSD, USA
Rami Melhem, University of Pittsburgh, USA
Timothy Pinkston, USC, USA
Chunming Qiao, State University of New York at Buffalo, USA
Sanguthevar Rajasekaran, University of Florida, USA
Sartaj Sahni, University of Florida, USA
Hong Shen, Griffith University, Australia
Ted Szymanski, McGill University, Montreal, Canada
Hugo Thienpont, Vrije Universiteit Brussel, Belgium
Jerry L. Trahan, Louisiana State University, USA
Ramachandran Vaidyanathan, Louisiana State University, USA
Yuanyuan Yang, University of Vermont, USA
Si Qing Zheng, University of Texas at Dallas, USA

Steering Committee Chair:
Afonso Ferreira, ENS Lyon, France

Steering Committee:
P. Chavel, IOTA, Orsay, France
T. Drabik, Georgia Tech, Metz, France and Atlanta, USA
S.C. Esener, UCSD, USA
P. Spirakis, CTI, Patras, Greece

Optical means are now widely used in telecommunication networks, and the evolution of optical and optoelectronic technologies tends to show that they could be successfully introduced in shorter distance interconnection systems such as parallel computers. These technologies offer a wide range of techniques that can be used in interconnection systems. But introducing optics in interconnect systems also means that specific problems have yet to be solved while some unique features of the technology must be taken into account in order to design optimal systems. Such problems and features include device characteristics, network topologies, packaging issues, compatibility with silicon processors, system level modeling.

The purpose of WOCS is two-fold. First, we hope to provide a good opportunity for the optical, architecture, and communication research communities to get together for a fruitful cross-fertilization and exchange of ideas. The goal is to bring the optical interconnects research into the mainstream research in parallel processing, while at the same time provide the parallel processing community with a more comprehensive understanding of the advantages and limitations of optics as applied to high-speed communications. In addition, we intend to assemble a group of major research contributors to the field of optical interconnects for assessing its current status, and identifying future directions.

WOCS will feature invited speakers, and several sessions of submitted papers. The presentations will cover the topics of:

- High-speed interconnections
- Optical interconnects
- Algorithms using optical interconnects
- Parallel optical architectures
- Reconfigurable optical interconnects and architectures
- Applications of optical interconnects
- Modeling of optical systems and applications
- Performance analysis and comparisons
- Packaging of optical interconnects
- System demonstrations
- Routing in optical networks

For further information, please contact:

Prof. Yi Pan
Computer Science Department
University of Dayton
Dayton, OH 45469-2160 USA.

Workshop 10: All Day Friday


Program Committee Chair:
Tao Yang, UC Santa Barbara

Steering Committee:
Afonso Ferreira, INRIA Sophia-Antipolis
José Rolim, University of Geneva

Program Committee:
Daniel Andresen, Kansas State University
Scott Baden, UC San Diego
Soumen Chakrabarti, IBM Almaden Research Center
Siddhartha Chatterjee, University of North Carolina
Ricardo Correa, DC/UFC, Brazil
Michel Cosnard, LORIA, France
Geoffrey Fox, Syracuse
Apostolos Gerasoulis, Rutgers University
Howard Ho, IBM Almaden Research Center
Oscar Ibarra, UC Santa Barbara
Vipin Kumar, University of Minnesota
Esmond Ng, Oak Ridge National Lab
Keshav Pingali, Cornell University
Sanjay Ranka, University of Florida
Joel Saltz, University of Maryland
Horst Simon, NERSC, Lawrence Berkeley Lab
Shanghua Teng, University of Illinois
Denis Trystram, IMAG, France
Herry Wijshoff, University of Leiden

Efficient parallel solutions have been found to many problems. However, there still exists a large class of problems - known as irregularly structured problems - that lack efficient solutions and systems support. This workshop on solving irregularly structured problems in parallel aims at fostering the cooperation among practitioners and theoreticians of the field. It is the sixth in the series, after Geneva, Lyon, Santa Barbara, Paderborn, and Berkeley.

Irregular'99 will feature invited talks and several sessions of submitted papers. The presentations will cover the following topics: mesh and sparse matrix computations, approximation and combinatorial optimization, parallel languages and models, compiler optimization and runtime systems, load balancing and scheduling, performance prediction and simulation, Internet computing and data-intensive applications.

Workshop papers will be included in the IPPS/SPDP Workshop Proceedings published by Springer-Verlag as part of their Lecture Notes in Computer Science (LNCS) Series. Extended versions of workshop papers will be solicited for a special journal edition and authors will receive information before or during the workshop. Previous proceedings of Irregular series appeared as LNCS 980, 1117, 1253 and 1457.

For further information, please contact:

Email: or see Web page at URL

Workshop 11: All Day Friday


Workshop Co-Chairs:

Giovanni Chiola, DISI, University of Genoa, Italy
Gianni Conte, University of Parma, Italy
Luigi V. Mancini, University of Rome "La Sapienza," Italy

Program Committee:
M. Baker, CSM, U. Portsmouth, UK
G. Chiola, DISI, U. Genoa
T.-C. Chiueh, CS Dept., SUNY S.B.
G. Conte, CE, U. Parma
H.G. Dietz, ECE, Purdue U.
W. Gentzsch, GENIAS Software GmbH
G. Iannello, DIS, U. Napoli
L.V. Mancini, DSI, U. Roma 1
T.G. Mattson, Intel Microcomp. Research Lab.
W. Rehm, Informatik, T.U. Chemnitz
P. Rossi, ENEA, Bologna
T. Sterling, CACR, Caltech, USA
C. Szyperski, Queensland U. of Tech.
Y. Tanaka, PDSP Lab, RWCP, Japan
D. Tavangarian, Informatik, U. Rostock
B. Tourancheau, LHPC/ENS, U. Lyon

Clusters composed of fast personal computers are becoming more and more attractive as cheap and efficient platforms for distributed and parallel applications. The main drawback of a standard NOW (Network Of Workstations) is the poor performance of the standard inter-process communication mechanisms based on RPC, sockets, TCP/IP, Ethernet. Such standard communication mechanisms perform poorly both in terms of throughput as well as message latency.

Recently, several prototypes developed around the world have proved that re-visiting the implementation of the communication layer of a standard operating system kernel, a low cost hardware platform composed of only commodity components, can scale up to several tens of processing nodes and deliver communication and computation performance exceeding the one delivered by the conventional high-cost parallel platforms.

Despite the importance of this break-through, that allows the use of inexpensive hardware platforms for efficient support of large/medium/fine grain parallel computation in a NOW environment, few papers describing their design and implementation still appear in the literature. Multiprogramming and co-scheduling of communicating processes so that "real applications" can be efficiently parallelized in NOW environments are still open research issues as well.

The PC-NOW workshop provides a forum where researchers and practitioners can discuss issues, results, and ideas related to the design of efficient NOWs based on commodity hardware and software components.

The program will consist of two keynote lectures - to be announced - and a number of contributed (25 minute) presentations including but not limited to:

- Experience with low-cost, high-performance NOW
- Low-cost communication hardware for personal computers
- Performance evaluation and benchmarks for NOW
- Porting of significant applications on low-cost NOW
- Efficient implementation of message passing libraries for NOW
- Parallel application environment for NOW
- Communication architectures
- Communication paradigms
- Industrial relevance

Invited Speakers:

There will be two invited speakers presenting state-of-the-art results in
the field as well as an overview of recent advances in the international
research community.

For further information, please contact:

Giovanni Chiola
DISI, University of Genoa
35 via Dodecaneso, 16146 Genoa, Italy
Vox: +39 010-353-6606
Fax: +39 010-353-6699

Workshop 12: All Day Friday


Workshop Chairs:

Dominique Mery, University Henri Poincare-Nancy 1 and IUF, France
Beverly Sanders, University of Florida, Gainesville, USA

Workshop Theme: Modeling and Proving

Program Committee:
Flemming Andersen, Tele Danmark R&D, Denmark
Mani Chandy, Department of Computer Science, Caltech, USA
Radhia Cousot, LIX-CNRS, Ecole Polytechnique, France
Pascal Gribomont, Institut MONTEFIORE, Universite de LIEGE, Belgium
Dominique Mery, Université Henri Poincaré & IUF, LORIA, France (CoChair)
Lawrence Paulson, Computer Laboratory, Cambridge University, UK
Xu Qiwen, International Institute for Software Technology, United Nations University, Macau
Catalin Roman, Department of Computer Science, Washington University, USA
Beverly Sanders, Department of Computer & Information Science & Engineering, University of Florida, USA (CoChair)
Ambuj Singh, Department of Computer Science, University of California at Santa Barbara, USA


Formal methods have been widely investigated in academic institutions and more recently have been applied in industry. They allow systems and their properties to be described precisely using mathematical notation. Algorithmic solutions are developed from the formal specification with the help of mathematical techniques and tools. Although they may be expensive to apply, formal methods are the only way to ensure that an implementation is correct with respect to a specification, and are thus an important tool for the development of reliable systems. The objective of the workshop is to gather people, both from academia and industry, who use and/or develop formal methods for parallel programming. FMPPTA'99 will emphasize two steps related to formal methods: the modeling phase where the problem is stated formally, and the proving phase that demonstrates the correctness of an implementation. As this workshop is a part of IPPS/SPDP, authors are strongly invited to use real case studies borrowed from parallel processing or distributed computing.

Invited Speakers:
(to be announced)

For further information, please contact:

FMPPTA'99/Dominique Mery
LORIA, Universite Henri Poincare-Nancy 1
Batiment LORIA, BP239
F-54506 Vandoe uvre-les-Nancy France
Vox: +33 3 83 59 20 14
Fax: +33 3 83 41 30 79

Workshop 13: All Day Friday


Workshop Co-Chairs:

Devesh Bhatt, Honeywell Technology Center, USA
Viktor Prasanna, Univ. of Southern California, USA

Program Committee:
Ashok Agrawala, Univ. of Maryland, USA
Bob Bernecky, NUWC, USA
Hakon O. Bugge, Scali Computer, Norway
Terry Fountain, University College London, UK
Richard Games, MITRE, USA
Farnam Jahanian, Univ. of Michigan, USA
Jeff Koller, USC/Information Sciences Institute, USA
Mark Linderman, USAF Rome Laboratory, USA
Craig Lund, Mercury Computer Systems, Inc., USA
Stephen Rhodes, Advanced Systems Architectures Ltd., UK
Samuel H. Russ, Mississippi State Univ., USA
Philip Sementilli, Hughes Missile Systems Co., USA
Behrooz Shirazi, University of Texas at Arlington, USA
Anthony Skjellum, Mississippi State Univ., USA
Lothar Thiele, Swiss Federal Institute of Technology, Switzerland
Chip Weems, Univ. of Massachusetts, USA
Sudhakar Yalamanchili, Georgia Tech., USA

Advisory Committee:
Keith Bromley, NRaD, USA
Dieter Hammer, Eindhoven Univ. of Technology, The Netherlands
David Martinez, MIT Lincoln Laboratory, USA
Jose Munoz, DARPA/ Information Technology Office, USA
Clayton Stewart, SAIC, USA
Lonnie Welch, Univ. of Texas at Arlington, USA

The International Workshop on Embedded HPC Systems and Applications (EHPC) is a forum for the presentation and discussion of approaches, research findings, and experiences in the applications of High Performance Computing (HPC) technology for embedded systems. Of interest are both the development of relevant technology (e.g., hardware, middleware, tools) as well as the embedded HPC applications built using such technology.

We hope to bring together industry, academia, and government researchers/users to explore the special needs and issues in applying HPC technologies to defense and commercial applications.

Topics of interest:

- Algorithms and applications such as radar signal processing, surveillance, automated target recognition
- Programming environments and development tools
- Performance modeling/simulation, partitioning/mapping and architecture trade-off
- Operating systems and middleware services, addressing real-time scheduling, fault-tolerance, and resource management
- Special-purpose architectures

EHPC'99 will feature technical papers, presentations, and an open discussion session. Proceedings will be published in a volume of Lecture Notes in Computer Science (LNCS) by Springer-Verlag.

For further information, please contact:

Devesh Bhatt
Honeywell Technology Center
3660 Technology Drive
Minneapolis, MN 55418, USA
Vox: +1 (612) 951-7316

Workshop 14: All Day Friday


Workshop Chair:

D.R. Avresky, Boston University, USA

Increasingly large parallel and distributed computing systems provide unique challenges to the researchers in dependable computing, especially because of the high failure rates intrinsic to these systems. While commercial and scientific companies share the need for massive throughput and low latency, dependability of service is also a concern. In addition to providing uninterrupted service, commercial systems must be free from data corruption. Achieving dependability in highly scalable parallel and distributed systems poses a considerable challenge. As the number of components increases, so does the probability of a component failure. Therefore, improved fault-tolerant technology is required for highly scalable parallel and distributed systems.

The goal of this workshop is to provide a forum for researchers and practitioners to discuss issues related to fault-tolerant parallel and distributed systems. All aspects of design, theory and realization of dependable network-based computing systems are of interest.

Topics of interest include, but are not limited to:

- Dependable distributed systems
- Fault-tolerant protocols for distributed systems
- Fault-tolerance in clusters of workstations and PCs
- Fault-tolerant interconnection networks
- Fault-tolerant parallel programming
- Using COTS for designing dependable network based computing systems
- Portable checkpointing for heterogeneous distributed systems
- Fault injection in parallel and distributed systems
- Dependability evaluation and validation of fault-tolerant parallel and distributed systems

Program Committee:
J. Bruck, Caltech, USA
B. Ciciani, University of Roma, Italy
F. Cristian, University of California, San Diego, USA
J. Hayes, University of Michigan, Ann Arbor, USA
R. Horst, Compaq Tandem Labs, USA
S. Hosseini, University of Wisconsin-Milwaukee, USA
D. Kaeli, Northeastern University, USA
M. Karpovsky, Boston University, USA
T. Katayama, AIST, Japan
I. Koren, University of Massachusetts, Amherst, USA
H. Levendel, Motorola, USA
Q. Li, Santa Clara University, USA
F. Lombardi, Northeastern University, USA
E. Maehle, University of Lubeck, Germany
K. Makki, UNLV, USA
M. Malek, Humboldt University, Germany
V. Morariu, CTC, USA
M. Raynal, IRISA, France
R. Vidale, Boston University, USA

The workshop is sponsored by the IEEE Computer Society Technical Committee on Parallel Processing.

For further information, please contact:

D.R. Avresky
Network Computing Lab
Dept. of ECE
Boston University
8 Saint Mary's St.
Boston, MA 02215
Vox: (617) 353-9850
Fax: (617) 353-6440

The selected papers will appear in the book, published by Kluwer Academic Publishers, MA, USA.

Workshop 15: All Day Friday


Workshop Chairs:

Vipin Kumar, University of Minnesota
Sanjay Ranka, University of Florida
Vineet Singh

Program Committee:
Alok Choudhary, Northwestern University
Umesh Dayal, HP
Ananth Grama, Purdue University
Robert Grossman, University of Chicago
Yike Guo, Imperial College, London
Jiawei Han, Simon Fraser University
Howard Ho, IBM
Bob Hiromoto, University of Texas, San Antonio
Chandrika Kamath, Lawrence Livermore National Lab
George Karypis, University of Minnesota
M. Kitsuregawa, University of Tokyo
Helene Kulsrud, IDA
Manavendra Misra, Colorado School of Mines
H. Simon, NERSC
David Skillicorn, Queens University
Jaideep Srivastava, University of Minnesota
Mohammed Zaki, RPI

The last decade has seen an explosive growth in database technology and the amount of data collected. Advances in data collection, use of bar codes in commercial outlets, and the computerization of business transactions have flooded us with lots of data. We have an unprecedented opportunity to analyze this data to extract more intelligent and useful information. Data mining is the efficient supervised or unsupervised discovery of interesting, useful, and previously unknown patterns from this data. Due to the huge size of data and amount of computation involved in data mining, high-performance computing is an essential component for any successful large-scale data mining application. This workshop will provide a forum for presentation of recent results in high-performance computing for data mining including applications, algorithms, software, and systems. Works which address issues in high performance computing and/or memory hierarchy are of interest.

Topics of interest include:

- Classification and regression
- Decision trees
- Association rules
- Dependency derivation
- Clustering
- Deviation detection
- Similarity search
- Bayesian networks

Important Dates:

Paper Submission: Feb. 15, 1999
Author Notification: March 15, 1999
Camera Ready Due: March 31, 1999

Paper Submission:

The workshop will feature contributed papers and invited papers in an
informal setting. To submit a paper for consideration, send 4 copies of
the manuscript to one of the workshop chairs. Electronic submissions
(postscript versions printable on 8.5 x 11 paper only) are strongly
encouraged. To guarantee consideration, manuscripts must be received by
Feb. 15, 1999, and must be no more than 5 pages excluding figures, tables,
and references. In the spirit of the workshop, submission of works in
progress are encouraged as well. A hard copy of the proceedings will be
available at the workshop. A copy of the proceedings will also be
available on the Web.

For up-to-date information about this workshop, please see

8 AM - 12 NOON
Tutorial 3

Nikola Serbedzija
GMD FIRST, Berlin, Germany

Who Should Attend:

The tutorial is meant for system designers, teachers, researchers, practitioners, and advanced students who want to gain better understanding of the design and development of Web-enabled systems. It will demonstrate (1) how to enrich Web sites with distributed software, (2) how to enable the existing applications for the Web use, and (3) how to develop a multi-media Java-based user interface for Web applications. There will be several running illustrations of Web-enabled systems with media-rich user interface. The attendee should be familiar with the World Wide Web and related technologies. No specific technical expertise is required, since the focus will be on design issues and principles rather than implementation details.

Course Description:

A Web-enabled system is a distributed system that uses a Web browser as a front-end. The goal of the tutorial is to explain principles of Web-enabled systems and provide basic understanding of software concepts, techniques and architectures needed for integrating new or existing applications into a Web-based distributed framework. The tutorial addresses a number of issues related to Web enabling technology like client/server and message-passing paradigms, basic Web principles (HTTP server properties, protocols, CGI, JavaScripts, etc.), dynamic collaboration, code migration, Java's remote method invocation, and multi-tier middleware architectures. Each concept will be illustrated with concrete examples, gradually constructing a case study that shows how to implement a Web-enabled application.


Nikola Serbedzija is a senior scientist at GMD FIRST (German National Research Center for Information Technology). His major research interest is the design of parallel and distributed systems for dedicated use in different application domains. He is the principal designer of the GoWeb system, an object-oriented middleware for enabling computing resources for use within the WWW. He has published numerous contributions in journals and proceedings on distributed and parallel systems, neurosimulations and Web-based computing. He has lectured at Technical University Berlin and has given a number of tutorials and special seminars. He received a Ph.D. in Computer Science from University of Belgrade in 1989. More information about the author and tutorial can be found at URL